1. Field of the Invention
The present invention relates to, for example, a NAND flash memory and more particularly to a semiconductor storage device capable of storing multilevel data into memory cells.
2. Description of the Related Art
In a NAND flash memory, a number of memory cells arranged in the row direction are connected to a corresponding word line and all or half of a number of memory cells arranged in the column direction are connected in series to form a NAND unit. The drain side of this NAND unit is connected to a corresponding bit line through a select gate. Each of the bit lines is connected a write and read latch circuit. All or half of the cells arranged in the row direction (e.g., 2 to 8-KB cells) are collectively written to or read from. In an erase operation, the threshold voltage of memory cells is made negative. Injection of electrons into memory cells in a write operation sets the threshold voltage positive (see, for example, Jpn. Pat. Appln. KOKAI No. 2004-192789).
With the NAND flash memory, a number of memory cells are connected in series; therefore, it is required to set non-selected cells to the on state in a read operation, in which case a read voltage (Vread) higher than the threshold voltage is applied to the gates of the cells. For this reason, the threshold voltage in a write operation does not have to exceed Vread. In a write sequence, it is necessary to repeatedly carry out a program operation and a program verify read operation for each bit to control the distribution of threshold voltages so that Vread is not exceeded. Accordingly, the write speed is lowered.
In addition, in order to store large amounts of data, multilevel memories have been developed in which one cell can store more than one bit. For example, in a case where one cell stores two bits, it is required to set four threshold distributions. In comparison with a memory in which one cell stores one bit, it is necessary to write so that each one of four threshold distributions becomes narrow. Therefore, the write speed becomes than that of the memory in which one cell stores one bit.
Therefore, in order to write to a high threshold, it is required to apply a high write voltage to a selected word line. However, non-writing cells which are connected to the same word line must not be written. It is therefore necessary to set (boot) the potential on the channel region high at the write time. To this end, it is only required to set the voltage (Vpass) on non-selected word lines to a high level. In this case, however, there arises a problem that cells which are not to be written to and which constitute a NAND unit together with cells to be written to are actually written to. For this reason, it is desired to set the potential on the non-selected word lines as low as possible and the potential on the channel region high. Thus, a semiconductor storage device has been demanded which can prevent erroneous writing to non-selected cells and write a plurality of threshold voltages at high speed without setting the potential (Vpass) high.